1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device utilizing alignment marks, as well as to a semiconductor device manufactured by the method. More particularly, the present invention relates to specifications concerning the dimensions of an alignment mark for use in chemical-mechanical polishing of a tungsten layer (hereinafter abbreviated as the xe2x80x9cW-CMP techniquexe2x80x9d), as well as to an improved process for improving the accuracy of alignment.
2. Background Art
Some conventional methods for manufacturing a semiconductor device utilizing alignment marks will be described.
First, conventional example 1 will be described.
FIGS. 8A to 8C are cross-sectional views showing an example method of forming an alignment mark during the course of the conventional method of manufacturing a semiconductor device.
As shown in FIG. 8A, according to a conventional method of manufacturing a semiconductor device, an interlayer oxide film 2 is deposited on a semiconductor substrate (wafer) 1 (or an aluminum interconnection 1 placed on a semiconductor substrate). The interlayer oxide film 2 is selectively etched by means of photolithography, thereby forming a normal contact 9 and an alignment mark 8. Further, a barrier metal 3 is formed over the interlayer oxide film 2, as well as on the normal contact 9 and the alignment mark 8, by means of sputtering. Tungsten 4 is deposited on the barrier metal layer 3 by means of the CVD technique.
As shown in FIG. 8B, the portion of the tungsten layer 4 and the portion of the barrier metal 3 that are placed on the interlayer oxide film 2, and a portion of the upper surface of the interlayer oxide film 2 are abraded by means of the W-CMP technique.
As shown in FIG. 8C, an additionally-stacked barrier metal layer 5 is formed over the entire surface of the wafer 1 by means of sputtering. An AlCu layer 6 and an antireflection-coating (ARC) film 7 are formed on the additionally-stacked barrier metal layer 5 by means of the sputtering technique. Subsequently, resist 10 is applied over the wafer 1 and is exposed.
The wafer is aligned during exposure through use of a laser beam or visible light. Thick metal layers (i.e., the ARC film 7, the AlCu layer 6, and the additionally-stacked barrier metal layer 5) lie immediately below the resist film 10. If no step is formed in the alignment mark 8, the surface of the wafer 1 becomes a completely mirrored surface, thus rendering an alignment operation impracticable.
Conventional example 2 will now be described.
FIGS. 9A to 9E are cross-sectional views showing an example method of forming an alignment mark carried out during the course of the conventional method of manufacturing a semiconductor device.
As shown in FIG. 9A, according to a method of manufacturing a conventional semiconductor device, an STI layer (a buried isolation layer or a trench isolation layer) 11, a gate oxide film 24, a gate electrode 12, a sidewall 13, and a CoSi layer 14 are formed on the semiconductor substrate 1 (Si substrate).
As shown in FIG. 9B, an oxide film is deposited on the substrate 1, and the oxide film is smoothed by means of the CMP technique (i.e., the oxide film CMP method), thereby forming an interlayer oxide film 15.
The corresponding wafer is subjected to photolithography, and contact holes 18 and a contact alignment mark 19 are formed by means of anisotropic dry etching.
As shown in FIG. 9C, a barrier metal layer 16 is formed by means of sputtering, and tungsten 17 is deposited over the surface of the wafer by means of the CVD technique.
As shown in FIG. 9D, portions of the tungsten layer 17 and top horizontal portions of a barrier metal layer 16 are abraded by means of the W-CMP technique, thus producing a tungsten plug 20. At this time, a step P appears in the contact alignment mark 19.
As shown in FIG. 9E, an additionally-stacked barrier metal layer 21, an AlCu layer 22, and an ARC film 23 are formed by means of the sputtering technique. At this time, the step P still remains in the contact alignment mark 19 in its present form.
In conventional example 2, the alignment mark 19 has a small step.
Conventional example 3 will now be described.
FIGS. 10A through 12C are cross-sectional views showing an example method of forming an alignment mark carried out during the course of the conventional method of manufacturing a semiconductor device.
FIGS. 10A through 10C are identical with FIGS. 8A through 8C showing example 1.
As shown in FIG. 11A, the ARC film 7, the AlCu layer 6, and the additionally-stacked barrier metal layer 5 are selectively etched by means of dry etching. At this time, as explained later with reference to FIG. 12A, an aluminum (Al) cap 28 serving as a cap of an alignment mark, an Al interconnection 30, and an underlying aluminum (Al) layer 29 which lies below a through hole alignment mark are formed.
As shown in FIG. 11B, an oxide film is deposited on the corresponding wafer, and the thus-deposited oxide film is smoothed by means of the CMP technique, thereby forming an interlayer oxide film 25.
The wafer is subjected to photolithography and dry etching. At this time, a through hole alignment mark 26 and a through hole 27 are formed.
As shown in FIG. 11C, a barrier metal layer 31 is formed by means of sputtering, and tungsten 32 is deposited by means of the CVD technique.
As shown in FIG. 12A, portions of the tungsten layer 32, those of the barrier metal layer 31, and those of the interlayer oxide film 25 are abraded by means of the W-CMP technique.
As shown in FIG. 12B, an additionally-stacked barrier metal layer 33, an AlCu layer 34, and an ARC layer 35 are formed by means of sputtering, and a resist film 36 is formed.
As shown in FIG. 12C, the ARC layer 35, the AlCu layer 34, and the additionally-stacked barrier metal layer 33 are selectively etched, thereby forming an Al electrode 37 and an alignment mark/cap aluminum (CAP-AL) layer 38.
In example 3, the depth of a step formed in the alignment mark 26 is determined by the process shown in FIG. 12A, and only a small step is formed. Further, the step is shallower than the thickness of the intermediate oxide film 25.
The present invention has been conceived to solve a drawback of the background art; that is, difficulty in forming a sufficient step in an alignment mark.
A problem which the present invention is to solve will be described by reference to FIGS. 13A to 13C.
As illustrated in FIGS. 13A to 13C, xe2x80x98Axe2x80x99 denotes an initial step formed in a tungsten layer 4; xe2x80x98Bxe2x80x99 designates the thickness of an interlayer dielectric film 2; xe2x80x98Cxe2x80x99 designates the width of an alignment mark; xe2x80x98Dxe2x80x99 designates the width of the top of the alignment mark after tungsten has been deposited on a wafer; xe2x80x98Exe2x80x99 denotes the diameter of a through hole; xe2x80x98Fxe2x80x99 denotes the thickness of the tungsten film; xe2x80x98Kxe2x80x99 denotes the amount of tungsten film to be abraded by means of the W-CMP technique; xe2x80x98Gxe2x80x99 denotes the thickness of an interlayer film after tungsten has been abraded by means of the W-CMP technique; xe2x80x98Hxe2x80x99 denotes a step of the alignment section after the tungsten film has been abraded by means of the W-CMP technique; and xe2x80x98Ixe2x80x99 denotes a step of the alignment section after an AlCu layer 6 and a barrier metal film 7 have been deposited on the wafer.
In a case where the step xe2x80x98Ixe2x80x99 of the alignment section does not have a given size, a laser beam or visible light, which is reflected during alignment operation, has a weak intensity, thus posing difficulty in detection of the edge of an alignment mark. As a result, alignment becomes impossible or accuracy of alignment is decreased greatly.
The present invention provides a method of maintaining the step.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, an interlayer dielectric film is formed on a semiconductor substrate. An opening for alignment purpose is formed in the interlayer dielectric film. A tungsten layer is formed on the interlayer dielectric film such that a depression is formed in the opening. The tungsten layer is abraded to thereby form an alignment step in the opening. Here, the interlayer dielectric film is formed such that an initial thickness of the interlayer dielectric film is greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, an interlayer dielectric film is formed on a semiconductor substrate. An opening for alignment purpose is formed in the interlayer dielectric film. A tungsten layer is formed on the interlayer dielectric film such that a depression is formed in the opening. The tungsten layer is etched so that thickness is reduced by a predetermined amount. The tungsten layer is abraded to thereby form an alignment step in the opening.
Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.